Summary of IIC communication protocol (detailed description of the complete process)

Introduction to IIC protocol

The IIC (inter-integrated Circuit integrated circuit bus) bus supports short-distance communication between devices and is used for the interface between the processor and some peripheral devices. It requires two signal lines to complete the exchange of information. A special process advantage of IIC is that the microcontroller only requires two general-purpose I/O pins and software to control the chip network. IIC was first developed and designed by Philips in 1982 and used on its own chips. At first, it only allowed 100Khz, 7-bit standard addresses. In 1992, the first public specification of IIC was released, adding a 400Khz fast mode and a 10-bit address extension. .

IIC agreement content

The IIC protocol divides transmitted messages into two types of frames:
Address frame – used by the master to indicate where the message is sent to the slave;
Data frame (single or continuous) – data sent from the master to the slave or data received from the slave. The unit of reading and writing at a time is 8 bits, with the high bit sent first
Note: IIC reading and writing are relative to master.
Data transfer on IIC bus
1. Regulations on data bit validity:
When the IIC bus is transmitting data, the data on the data line must remain stable while the clock signal is high. Only when the clock level is low, the high or low state of the data line is allowed to change. .
That is, the data needs to be ready before the rising edge of the clock line SCL arrives, and must remain stable before the falling edge arrives.
2. Idle state:
When the data line SDA and the clock line of the IIC bus are at high level at the same time, it is defined as the idle state of the bus. At this time, the output stage field effect transistors of each device are in a cut-off state, that is, the bus is released, and the level is pulled high by the pull-up resistors of the two signal lines.
3. Start and stop signals:
When SCL is high level, the change of the SDA signal line from high level to low level indicates the start signal; during the period of SCL being high level, the change of SDA signal line from low level to high level indicates the termination signal.
SDA: low to high – start signal
SDA: high to low – termination signal
Both the start signal and the stop signal are sent by the host. After the start signal is generated, the bus is in an occupied state. After the stop signal is generated, the bus is in an idle state.

4. Response signal:
Every time the transmitter sends a byte (8 bits), it releases the data line during clock pulse 9, and the receiver feeds back a response signal.
When the response signal is low level, it is specified as a valid response (ACK, referred to as the response bit), indicating that the receiver has successfully accepted the byte
When the acknowledge bit is high, it is specified as a non-acknowledge signal (NACK), which generally indicates that the receiver failed to receive the byte successfully.
The requirement for an effective response signal ACK for feedback is that the receiver pulls the data line SDA low during the low level before the 9th clock pulse, and ensures a stable low level during the high level of this clock. If the receiver is the master, after it receives the last byte, it sends a NACK signal to notify the controlled transmitter to end the data transmission, and releases the data line SDA so that the master receiver sends a stop signal P .
5. Data transmission format:
(1) Byte transmission and response: Each byte must be guaranteed to be 8 bits in length. When transmitting data, the highest bit (MSB) is transmitted first, and each transmitted byte must be followed by a 1-bit response bit (that is, each frame of data has a total of 9 bits)
(2) Each bit of data transmitted on the IIC bus has a corresponding clock pulse (or synchronous control), that is, with the cooperation of the SCL serial clock, each bit of data is serially transmitted bit by bit on the SDA. The transmission of data bits is edge triggered.
6. Bus addressing:
(1) The IIC protocol stipulates the use of a 7-bit addressing byte (the addressing byte is the first byte after the start signal). Its bit definitions are as follows:
| bit | 7 | 6 | 5 | 4 |3 |2|1| 0|
D7 ~ D1 bits constitute the slave address.
The D0 bit is the direction of data transmission, 0 indicates that the host reads data from the slave.
(2) The master device writes registers to the slave device. The data transmission format is as follows:

1) First, the host sends a start signal,
2) Then the host broadcasts the slave address on the data line
3) Determine the direction of data transmission (reading or writing)
4) “A” represents response, indicating that the host has found the slave.
5) The host sends a byte of data, and after the slave receives it, it will return a response signal to the host until the host completes sending the data, or the slave returns a NACK signal, indicating that the slave will no longer receive the data sent by the host. The host sends a stop signal. This data transfer is completed.
(2) The host reads the slave register value:

1) First, the host sends a start signal
2) The host then broadcasts the address on the data bus
3) Determine the data transmission direction (read 1)
4) The slave returns an “A” for response, indicating that the host has found the slave.
5) The slave returns the read data
6) The host returns a response signal, indicating that it successfully received a data sent from the slave.
7) When the host completes receiving the data, it returns a non-response signal “NACK”, the slave releases the data bus, and then the host sends a “P” signal to indicate the end of this data transmission.

1) The host first generates the START signal
2) Then send a slave address immediately. Note that the 8th bit of the address is 0 at this time, indicating that the command is written to the slave.
3) The master waits for the slave’s response signal (ACK)
4) When the host receives the response signal, it sends the address to be accessed and continues to wait for the response signal from the slave.
5) When the host receives the response signal, the host needs to change the communication mode (the host will change from sending to receiving, and the slave will change from receiving to sending), so the host resends a start signal, and then sends a slave address. Note that the 8th bit of the address is 1 at this time, indicating that the host is set to receive mode and starts reading data.
6) The host waits for the response signal from the slave. When the host receives the response signal, it can receive 1 byte of data. When the reception is completed, the host sends a non-response signal to indicate that it is no longer receiving data.
7) The host then generates a stop signal to end the transmission process.

Related Posts

Use the make tool to compile all .c in any directory and link & specify the output directory

Summary of digital and electronic knowledge points

Teach you step by step how to transplant openharmony3.0 to stm32 (liteos_m)

[STM32] KEIL engineering modifications for different STM32 chips (taking ZET6 to adapt C8T6 as an example)

STM32+ESP8266+MQTT connects to Alibaba Cloud server (3. AT command connects to Alibaba Cloud platform)

Shenzhou Loongson GSC3290 adapted to Yutai YT8521S operating instructions

Based on the 51 tracking car (the first project for beginners!!!)

Robomaster wheel motion calculation

Leave a Reply

Your email address will not be published. Required fields are marked *

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <s> <strike> <strong>