[FPGA]RGMII interface

Table of contents

1. RGMII interface overview

2. Introduction to RGMII interface

2.1 MII inlet

2.2 RMII interface

2.3 GMII interface

2.4 RGMII interface

1. RGMII interface overview

Ethernet communication is inseparable from the support of the physical layer PHY chip. There is an interface between the Ethernet MAC and PHY. Commonly used interfaces include MII, RMII, GMII, RGMII, etc.
MII(Medium Independent Interface, Media Independent Interface): MII supports 10Mbps and 100Mbps operations, and the data bit width is 4 bits

  • At 100Mbps transmission rate, the clock frequency is 25Mhz
  • At 10Mbps transmission rate, the clock frequency is 2.5Mhz

RMII(Reduced MII): RMII is a simplified version of MII, the data bit width is 2 bits

  • At 100Mbps transmission rate, the clock frequency is 50Mhz
  • At 10Mbps transmission rate, the clock frequency is 5Mhz

GMII(Gigabit MII): The GMII interface is backward compatible with the MII interface, supports 10Mbps, 100Mbps and 1000Mbps operations, and the data bit width is 8 bits

  • At 1000Mbps transmission rate, the clock frequency is 125Mhz
  • At 100Mbps transmission rate, the clock frequency is 25Mhz
  • At 10Mbps transmission rate, the clock frequency is 2.5Mhz

RGMII(Reduced GMII): RGMII is a simplified version of GMII, with a data bit width of 4 bits

  • At a transmission rate of 1000Mbps, the clock frequency is 125Mhz, and data is sampled simultaneously on the upper and lower edges of the clock.
  • At 100Mbps transfer rate, clock frequency is 25MHz, single clock edge sampling
  • At 10Mbps transfer rate, the clock frequency is 2.5MHz, sampling on a single clock edge

In Gigabit Ethernet, commonly used interfaces are RGMII and GMII interfaces. The advantage of the RGMII interface is that it is suitable for 10M/100M/1000Mbps communication rates at the same time and occupies a small number of pins. However, the RGMII interface also has its shortcomings, that is, the clock, control and data lines need to be of equal length as much as possible during PCB wiring, and the timing constraints are relatively stricter.

2. Introduction to RGMII interface

2.1 MII inlet

That is, the media independent interface, the data bit width is 4 bits, the clock frequency is 25MHz at the 100Mbps rate; the clock frequency is 2.5MHz at the 10Mbps rate

ETH_RXC: Receive data reference clock, ETH_RXC is provided by the PHY side.

ETH_RXDV: Receive data valid signal, high level is valid.

ETH_RXER: Receive data error signal, active high level.

ETH_RXD: Four-bit parallel receiving data line, when ETH_RXDV is high level and ETH_RXER is low level, the data is valid.

ETH_TXC: Transmit reference clock, ETH_TXC is provided by the PHY side.

ETH_TXEN: Transmit data valid signal, high level is valid.

ETH_TXER: Transmitting data error signal, high level is active.

ETH_TXD: Four-bit parallel transmission data line, when ETH_TXEN is high level and ETH_TXER is low level, the data is valid.

2.2 RMII interface

That is, a simplified media independent interface, the data bit width is 2 bits, at the 100Mbps rate, the clock frequency is 50MHz; at the 10Mbps rate, the clock frequency is 5MHz

REF_CLK: Reference clock

CRS_DV: CRS and DV multiplexing interface

ETH_RXER: Receive data error signal, active high level.

ETH_RXD: Two-bit parallel receive data line.

ETH_TXEN: Transmit data valid signal, high level is valid.

ETH_TXD: Two-bit parallel transmission data line

2.3 GMII interface

That is, a gigabit media independent interface with a data bit width of 8 bits. At 1000Mbps rate, the clock frequency is 125MHz; at 100Mbps rate, the clock frequency is 25M; at 10Mbps rate, the clock frequency is 2.5MHz

ETH_RXC: Receive data reference clock, ETH_RXC is provided by the PHY side.

ETH_RXDV: Receive data valid signal, high level is valid.

ETH_RXER: Receive data error signal, active high level.

ETH_RXD: Eight-bit parallel receiving data line, when ETH_RXDV is high level and ETH_RXER is low level, the data is valid. (4 digits of data are valid)

ETH_TXC: Transmit reference clock, ETH_TXC is provided by the PHY side.

ETH_TXEN: Transmit data valid signal, high level is valid.

ETH_TXER: Transmitting data error signal, high level is active.

ETH_TXD: Eight-bit parallel transmission data line, when ETH_TXEN is high level and ETH_TXER is low level, the data is valid. (4 digits of data are valid)

2.4 RGMII interface

That is, a simplified gigabit media independent interface, the data bit width is 4 bits, at 1000Mbps rate, the clock frequency is 125MHz; at 100Mbps rate, the clock frequency is 25M; at 10Mbps rate, the clock frequency is 2.5MHz

REF_CLK: Reference clock

ETH_RXCTL (ETH_RX_DV): Receive data control signal.

ETH_RXD: Four-bit parallel receive data line.

ETH_TXCTL (ETH_TXEN): Send data control signal.

ETH_TXD: four-bit parallel transmit data line

The ETH_TXCTL and ETH_RXCTL control signals also use DDR to transmit two bits of control signals in one clock cycle, namely the rising edge transmit/receive data enable (TX_EN/RX_DV) signal, the falling edge transmit/receive enable signal and the error signal. XOR values ​​(TX_ERR xor TX_EN, RX_ERR xor RX_DV).
 

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