Communication protocol (AXI)

1. Introduction to AXI

The SoC on-chip bus is still in the development stage and is not as mature as the microcomputer bus. There is currently no unified standard. Therefore, major manufacturers and organizations have launched their own standards in order to occupy a place in the future SoC on-chip bus standards. ARM launched its own bus in 1995 – AMBA (Advanced Microcontroller Bus Architecture, advanced microprocessor bus architecture). It is independent of processor and manufacturing process technology, enhances the reusability of peripherals and system macro cells in various applications, and is very suitable for the requirements of modern large-scale integrated circuit design automation.

A new bus has been added in AMBA3.0 – AXI (Advanced eXtensible Interface, advanced expansion interface). It is an on-chip bus designed for high performance, high bandwidth, and low latency. Its bus structure is shown in Figure 1. Its address/control and data phases are separated, supporting unaligned data transmission. At the same time, in burst transmission, only the first address is required, while separate read and write data channels, and supports significant transfer access and out-of-order access. And it is easier to achieve timing closure. AXI is a new high-performance protocol in AMBA. AXI technology enriches the existing AMBA standard content to meet the needs of ultra-high performance and complex SoC design.

AXI three types
AXI4(AXI4-full): Used for high-performance memory mapping requirements; (memory mapping: when the host performs read and write operations on the slave, it specifies a target address. This address corresponds to the address of the system storage space, indicating read and write operations on the space).
AXI4-Lite:Simplified version of the AXI4 interface for low-throughput memory-mapped communication.
AXI4-Stream(ST): Used for high-speed streaming data communication.

Advantages of AXI:
High productivity,
Flexibility: AXI4 (supports burst 256) and AXI4-Lite (1 data) are memory mapped
AXI4-ST is not memory mapped and its burst length is not limited.

2. How AXI works

AXI4 and AXI4-Lite contain 5 independent channels
Read address channel
Read data channel
write address channel
write data channel
write response channel

AXI4: Since the read and write address channels are separated, bidirectional simultaneous transmission is supported; the maximum burst length is 256
AXI4-Lite: Similar to AXI4, but does not support burst transmission
AXI4-Stream: There is only a single data channel, which is similar to the write data channel of AXI4; the burst length is not limited.

Read transaction graph

Write transaction diagram

AXI InterConnect and AXI SmartConnect
Both ip cores are used to connect single/multiple memory mapped AXI Master and single/multiple memory mapped AXI Slave

3. AXI channel definition

Each independent channel contains a set ofinformation signalVALID signalandREADY signal, used to provide a two-way handshake mechanism.
The information source uses the VALID signal to indicate when the current channel address, data and control information are valid, and the destination uses the READY signal to indicate when the information can be received. Both the read data channel and the write data channel include aLAST signal, used to represent the last data transmitted.
Both the read data channel and the write data channel contain their own address channels, which carry the address and information required for the request.
The read data channel is sent from the slave to the host, including read data and read corresponding information. The read response signal is used to indicate whether the read transfer operation is completed.
The write data channel is sent from the master to the slave, containing the write data, and then uses the WSTRB signal to indicate which byte of the current data is valid.
The write response channel is sent from the slave to the host and contains the write response signal to indicate whether the current write operation is completed.

4. AXI bus signal level description

The AXI bus, like other buses, has many signals, including global signals, write address channel signals, write data channel signals, write response channel signals, read address channel signals, read data channel signals, and low-power interface signals. All tables in this chapter use a 32-bit data bus, a 4-bit write data gate, and a 4-bit ID segment.
1. Global signal

ACLKClock sourceglobal clock signal
ARESETnReset sourceGlobal reset signal, active low level

2. Write address channel signal

AWID[3:0]HostWrite address ID. This signal is the ID tag of the write address signal group, which specifies the sequence of some special transmission tasks.
AWADDR[31:0]HostWrite the address.
AWLEN[3:0]HostThe length of the burst write. This length determines the number of data transferred by burst writing.
AWSIZE[2:0]HostBurst write size.
AWBURST[1:0]HostType of burst writing.
AWLOCK[1:0]HostLock type.
AWCACHE[3:0]HostCache type. This signal indicates the bufferable, cacheable, write-through, write-back, and allocate attributes information of the transaction.
AWPROT[2:0]HostProtection type.
AWVALIDHostThe write address is valid. 1 = Address and control information are valid. 0 = Address and control information are invalid, this signal will remain until AWREADY goes high.
AWREADYequipmentHave your address ready. This signal is used to indicate that the device is ready to accept address and control information. 1 = Device is ready, 0 = Device is not ready

3. Write data channel signal

WID[3:0]HostWrite ID tag, the value of WID must match the value of AWID
WDATA[31:0]Hostwritten data.
WSTRB[3:0]HostWrite valve. The interval marked by WSTRB[n] is WDATA[(8n)+7:(8n)]
WLASTHostThe last data written.
**WVALID**HostWrite is valid, 1 = write data and valve are valid, 0 = write data and valve are invalid
WREADYequipmentReady to write. Indicates that the device is ready to receive data, 1 = device is ready, 0 = device is not ready

4. Write response channel signal

BID[3:0]equipmentResponse ID. This value must match the value of AWID.
BRESP[1:0]equipmentWrite response. This signal indicates the status of the write transaction. Possible responses: OKAY, EXOKAY, SLVERR, DECERR.
BVALIDequipmentThe write response is valid. 1 = Write response is valid. 0 = invalid write response
BREADYHostAccept response ready. This signal indicates that the host has been able to accept response information. 1 = Host is ready. 0 = Host is not ready

5. Read the address channel signal

ARID[3:0]HostRead address ID.
ARADDR[31:0]HostRead address.
ARLEN[3:0]HostBurst read length.
ARSIZE[2:0]HostBurst read size.
ARBURST[1:0]HostBurst read type.
ARLOCK[1:0]HostLock type.
ARCACHE[3:0]HostCache type.
ARPROT[2:0]HostProtection type.
ARVALIDHostThe read address is valid. The signal remains active until ARREADY is high. 1 = Address and control information are valid. 0 = Address and control information are invalid
ARREADYequipmentRead address ready. Indicates that the device is ready to accept data. 1 = Device is ready. 0 = Device is not ready

6. Read the data channel signal

RID[3:0]equipmentRead ID tag. The value of RID must match the value of ARID.
RDATA[31:0]equipmentRead data.
RRESP[1:0]equipmentRead response. This signal indicates the status of the read transfer: OKAY, EXOKAY, SLVERR. DECERR.
RLASTequipmentRead the last data transferred by the transaction
RVALIDequipmentReading data is valid. 1 = Read data is valid. 0 = The read data is invalid.
RREADYHostReady to read data. 1 = Host is ready. 0 = Host is not ready

suddenreadThe timing diagram is as follows:
After the address appears on the address bus, the transferred data will appear on the read data channel. The device keeps VALID low until the read data is valid. In order to indicate the completion of a burst read and write, the device uses the RLAST signal to indicate the last transmitted data.

The device will process the second burst of read data after the first burst of read is completed. This means that the host initially sent two addresses to the device. The device does not start processing the data at the second address until it has completely processed the data at the first address.

suddenWriteThe timing diagram is as follows:
At the beginning of this process, the host sends address and control information to the write address channel, and then the host sends each write data to the write data channel. When the host sends the last data, the WLAST signal goes high. When the device has received all the data, it sends a write response back to the host to indicate that the write transaction is complete.

5. Handshake mechanism

All five channels transmit address, data and control information through the same VALID/READY handshake process. The two-way handshake mechanism means that when data is transmitted between the master and the slave, the transmission rate can be controlled. The transmission will only occur when VALID and READY are high at the same time.

All 5 channels use the same VALID/READY handshake mechanism to transmit data and control information. The transmission source generates the VLAID signal to indicate when data or control information is valid. The destination source generates a READY signal to indicate that it is ready to receive data or control information. The transfer occurs when the VALID and READY signals are high at the same time. There are three relationships between the occurrence of VALID and READY signals.

At the arrow information transfer occurs.
(2) READY goes high first and then VALID goes high. The timing diagram is as follows:

Also at the arrow information transfer occurs.
(3) The VALID and READY signals become high at the same time. The timing diagram is as follows

In this case, the information transfer occurs immediately, as indicated by the arrow in the figure.
2. Relationship between channels

The relationship between address, read, write and write response channels is flexible.

For example, write data can appear on an interface earlier than the write address associated with it. It is also possible that writing data and writing address occur in one cycle.

Two relationships must be maintained:

(1) Reading data must always follow the address associated with its data.

(2) A write response must always appear last in the write transaction with which it is associated.

3. Dependencies between channel handshake signals
The read transaction handshake dependencies are as follows:

The single arrow does not indicate a sequential dependency relationship, but the double arrow indicates a dependency relationship.
(1) The device can give the ARREADY signal when ARVALID appears, or it can give the ARREADY signal first and then wait for the ARVALID signal.

(2) However, the device must wait for both the ARVALID and ARREADY signals to be valid before giving the RVALID signal and starting data transmission.

The write transaction handshake dependencies are as follows:

(1) The host must not be able to wait for the device to give the AWREADY or WREADY signal before giving the AWVALID or WVLAID signal.

(2) The device can wait for the signal AWVALID or WVALID to be valid or both before giving the AWREADY signal.

(3) The device can wait for the AWVALID or WVALID signal to be valid or both signals to be valid before giving the WREADY signal.


Suitable for reading and writing some simple control registers when the full functionality of AXI4 is not required.

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